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| (R) STV60NE06-16 N - CHANNEL 60V - 0.013 - 60A PowerSO-10 STripFETTM POWER MOSFET PRELIMINARY DATA T YPE STV60NE06-16 s s s s s V DSS 60 V R DS(on) < 0.016 ID 60 A TYPICAL RDS(on) = 0.013 EXCEPTIONAL dv/dt CAPABILITY 100% AVALANCHE TESTED LOW GATE CHARGE 100 oC APPLICATION ORIENTED CHARACTERIZATION 10 DESCRIPTION This Power Mosfet is the latest development of STMicroelectronics unique "Single Feature SizeTM" strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalance characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s SOLENOID AND RELAY DRIVERS s MOTOR CONTROL, AUDIO AMPLIFIERS s DC-DC & DC-AC CONVERTERS s AUTOMOTIVE ENVIRONMENT (INJECTION, ABS, AIR-BAG, LAMPDRIVERS, Etc. ) 1 PowerSO-10 INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol V DS V DGR V GS ID ID I DM (*) P tot dv/dt Ts tg Tj May 2000 Parameter Drain-source Voltage (VGS = 0) Drain- gate Voltage (R GS = 20 k) G ate-source Voltage Drain Current (continuous) at Tc = 25 C Drain Current (continuous) at Tc = 100 C Drain Current (pulsed) T otal Dissipation at Tc = 25 C Derating Factor Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature o o o Value 60 60 20 60 42 240 150 1 6 -65 to 175 175 ( 1) ISD 60 A, di/dt 300 A/s, VDD V(BR)DSS, Tj TJMAX Un it V V V A A A W W /o C V/ns o o C C 1/6 (*) Pulse width limited by safe operating area STV60NE06-16 THERMAL DATA R thj -case Rthj -amb R thc-sink Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature F or Soldering Purpose 1 62.5 0.5 300 C/W oC/W o C/W o C o AVALANCHE CHARACTERISTICS Symbo l IAR E AS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max, < 1%) Single Pulse Avalanche Energy (starting Tj = 25 o C, ID = IAR , V DD = 25 V) Max Value 60 350 Unit A mJ ELECTRICAL CHARACTERISTICS (TJ = - 40 to 150 oC unless otherwise specified) OFF Symbo l V (BR)DSS I DSS IGSS Parameter Drain-source Breakdown Voltage Test Con ditions I D = 250 A V GS = 0 Min. 60 1 10 100 Typ. Max. Unit V A A nA V DS = Max Rating Zero Gate Voltage Drain Current (V GS = 0) V DS = Max Rating Gate-body Leakage Current (VDS = 0) V GS = 20 V T c =125 oC ON () Symbo l V GS(th) R DS(on) I D(o n) Parameter Gate Threshold Voltage V DS = V GS Static Drain-source On Resistance On State Drain Current V GS = 10V Test Con ditions ID = 250 A ID = 40 A 60 Min. 2 Typ. 3 0.013 Max. 4 0.016 Unit V A V DS > ID(o n) x R DS(on )ma x V GS = 10 V DYNAMIC Symbo l g f s () C iss C os s C rss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Con ditions V DS > ID(o n) x R DS(on )ma x V DS = 25 V f = 1 MHz I D =30 A V GS = 0 Min. 20 Typ. 35 4600 580 140 Max. Unit S pF pF pF 2/6 STV60NE06-16 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbo l t d(on) tr Qg Q gs Q gd Parameter Turn-on Time Rise Time Total G ate Charge Gate-Source Charge Gate-Drain Charge Test Con ditions V DD = 30 V I D = 30 A R G =4.7 V GS = 10 V (see test circuit, figure 3) V DD = 48 V I D = 60 A V GS = 10 V Min. Typ. 40 125 115 25 40 Max. 60 180 160 Unit ns ns nC nC nC SWITCHING OFF Symbo l tr (Voff) tf tc Parameter Off-voltage Rise T ime Fall T ime Cross-over Time Test Con ditions V DD = 48 V I D = 60 A R G =4.7 V GS = 10 V (see test circuit, figure 5) Min. Typ. 15 150 180 Max. 25 210 260 Unit ns ns ns SOURCE DRAIN DIODE Symbo l ISD I SDM (*) V SD () t rr Q rr I RRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 60 A V GS = 0 100 0.4 8 I SD = 60 A di/dt = 100 A/s o Tj = 150 C V DD = 30 V (see test circuit, figure 5) Test Con ditions Min. Typ. Max. 60 320 1.5 Unit A A V ns C A () Pulsed: Pulse duration = 300 s, duty cycle 1.5 % (*) Pulse width limited by safe operating area 3/6 STV60NE06-16 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 4/6 STV60NE06-16 PowerSO-10 MECHANICAL DATA DIM. MIN. A A1 B c D D1 E E1 E2 E3 E4 e F H h L q 0 o mm TYP. MAX. 3.65 0.10 0.60 0.55 9.60 7.60 9.50 7.40 7.60 6.35 6.10 1.27 1.25 13.80 0.50 1.20 1.70 8 o inch MIN. 0.132 0.000 0.016 0.013 0.370 0.291 0.366 0.283 0.283 0.240 0.232 0.050 1.35 14.40 1.80 0.049 0.543 0.002 0.047 0.067 0.071 0.053 0.567 TYP. MAX. 0.144 0.004 0.024 0.022 0.378 0.300 0.374 0.291 0.300 0.250 0.240 3.35 0.00 0.40 0.35 9.40 7.40 9.30 7.20 7.20 6.10 5.90 B 0.10 A B 10 = H = A F A1 = 6 = = = E = 1 5 = E2 E3 E1 E4 = = A = SEATING PLANE DETAIL "A" e 0.25 M B C Q h D = D1 = = = SEATING PLANE = A1 L DETAIL "A" 0068039-C 5/6 STV60NE06-16 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 6/6 |
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